Content
# PLC_Conversion_Estimate_By_Routine.pdf
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## Summary
This document provides a detailed engineering estimate for converting an Allen-Bradley MicroLogix 1400 PLC program to a new, unspecified PLC platform. It breaks down the effort by routine, covering control logic recreation, tag/address translation, timers, counters, interlocks, and fault/warning annunciation, with a total estimated effort of 33 hours focused on offline development and basic validation. The routines include motor control, wash sequencing, filler/capper operation, real-time clock handling, and fault/warning management.
## Content
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PLC Program Conversion Estimate (by Routine)
Source program: Allen-Bradley MicroLogix 1400 (RSLogix 500). Target: new PLC architecture (vendor/platform
TBD).
Total Estimated Engineering Effort: 33 hours
Assumptions and what is included
• Re-create the existing control intent and sequence logic (not a redesign of the process).
• Translate data tables and addressing (I:, O:, B3/B10/B11, N7, T4/T14, C5, RTC) into the target PLC tag
structure.
• Re-create timers/counters, one-shots, interlocks, and basic fault/warning annunciation as implemented today.
• Offline development plus code review and unit test; limited dry-run logic validation (no full site commissioning
in this estimate).
Estimate breakdown
Routine
Rungs
Primary tags/addresses (typical)
Complexity Hours
Justification
Initial setup and prep
—
Project scaffolding, tag mapping plan, I/O map import, naming conventions
Medium
2.0
Set up target project, create base tag structure
MAIN
24
B3, B11, S:1, JSR structure
Medium
3.0
Top-level scan orchestration (JSRs), first-scan
INPUTS
24
I:0/I:1 → internal bits/words; MOV mapping
Medium
2.0
Input mapping and conditioning; establish cons
MOTORS
4
Motor start/stop bits; basic interlocksLow
1.0
A few simple motor interlocks and run status lo
TIMER_PRESET
7
N7 → timer presets (MOV) / HMI setpoints
Low–Medium
2.0
Preset management refactor to target timer str
WASH_LOAD
19
Step bits, timers, counters, permissives
High
4.0
Sequenced load logic with step progression, dw
WASH_CNTRL
27
Counters, multiple timers, manual/auto branching
High
6.0
Core washer sequencing and bottle handling lo
FILLER_CAP
22
Timers, solenoids, debounce, interlocks
High
4.0
Filler/capper sequencing, timing windows, debo
RTC_CLOCK
4
RTC ↔ clock display tags (MOV/CPW)
Low
1.0
Clock set/copy logic; adapt to target PLC RTC
WARNINGS
9
Warning word/bit mapping; timing filters
Medium
3.0
Warning conditions with timing/filters and mapp
FAULTS
10
Fault word/bit mapping; latching/reset behavior
Medium
3.0
Fault aggregation and system fault state; ensu
OUTPUTS
23
O: mapping; permissives; fault inhibits
Medium
2.0
Output mapping and final permissives; verify e
Total: 33.0 hours
Notes
• Hours reflect translation effort: understand intent, map tags, re-implement instructions, and basic offline
validation.
• High-complexity routines are driven by step-based sequencing, multiple timers/counters, and manual/auto
branching.
• If the target PLC requires a fundamentally different design paradigm (SFC/AOIs/OO), effort may increase.
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